Port details on branch 2022Q2 |
- yosys Yosys Open SYnthesis Suite
- 0.40 cad =0 0.39Version of this port present on the latest quarterly branch.
- Maintainer: yuri@FreeBSD.org
- Port Added: 2020-01-04 18:47:36
- Last Update: 2024-04-11 08:17:20
- Commit Hash: 4118ab9
- License: ISCL
- WWW:
- https://yosyshq.net/yosys/
- Description:
- Yosys is a framework for Verilog RTL synthesis. It currently has
extensive Verilog-2005 support and provides a basic set of synthesis
algorithms for various application domains.
- ¦ ¦ ¦ ¦
- Manual pages:
- FreshPorts has no man page information for this port.
- pkg-plist: as obtained via:
make generate-plist - Dependency lines:
-
- To install the port:
- cd /usr/ports/cad/yosys/ && make install clean
- To add the package, run one of these commands:
- pkg install cad/yosys
- pkg install yosys
NOTE: If this package has multiple flavors (see below), then use one of them instead of the name specified above.- PKGNAME: yosys
- Flavors: there is no flavor information for this port.
- distinfo:
- TIMESTAMP = 1712808116
SHA256 (YosysHQ-yosys-yosys-0.40_GH0.tar.gz) = c1d42ad90d587b587210b40cf3c5584e41e20f656e8630c33b6583322e8b764e
SIZE (YosysHQ-yosys-yosys-0.40_GH0.tar.gz) = 2802706
Packages (timestamps in pop-ups are UTC):
- Dependencies
- NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.
- Build dependencies:
-
- abc : cad/abc
- bash : shells/bash
- gawk : lang/gawk
- bison : devel/bison
- gmake>=4.4.1 : devel/gmake
- pkgconf>=1.3.0_1 : devel/pkgconf
- python3.9 : lang/python39
- Test dependencies:
-
- iverilog : cad/iverilog
- python3.9 : lang/python39
- Runtime dependencies:
-
- xdot : x11/py-xdot@py39
- bash : shells/bash
- yices_smt2 : math/yices
- python3.9 : lang/python39
- Library dependencies:
-
- libffi.so : devel/libffi
- libtcmalloc.so : devel/google-perftools
- libreadline.so.8 : devel/readline
- libtcl86.so : lang/tcl86
- This port is required by:
- for Build
-
- cad/qflow
- cad/yosys-ghdl-plugin
- cad/yosys-systemverilog
- devel/lattice-ice40-examples-hx1k
- devel/lattice-ice40-examples-hx8k
- for Run
-
- cad/py-edalize
- cad/qflow
- cad/symbiyosys
- cad/yosys-ghdl-plugin
- cad/yosys-systemverilog
- devel/lattice-ice40-tools
Configuration Options:
- ===> The following configuration options are available for yosys-0.40:
TCMALLOC=on: Use the tcmalloc memory allocation library
====> Install SAT solvers
CVC5=off: CVC SAT Solver
YICES=on: Yices SAT Solver
Z3=off: Z3 SAT Solver
===> Use 'make config' to modify these settings
- Options name:
- cad_yosys
- USES:
- bison compiler:c++11-lang gmake pkgconfig python readline shebangfix tcl
- FreshPorts was unable to extract/find any pkg message
- Master Sites:
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