non port: cad/verilator/pkg-plist |
Number of commits found: 21 |
Sunday, 25 Feb 2024
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08:04 Yuri Victorovich (yuri)
cad/verilator: update 5.020 → 5.022
Reported by: portscout
a40e7b1 |
Monday, 29 Jan 2024
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19:54 Muhammad Moinur Rahman (bofh)
cad/verilator: Moved man to share/man
Approved by: portmgr (blanket)
213355e |
Tuesday, 2 Jan 2024
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06:53 Yuri Victorovich (yuri)
cad/verilator: update 5.018 → 5.020
Reported by: portscout
7caf409 |
Wednesday, 1 Nov 2023
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16:57 Yuri Victorovich (yuri)
cad/verilator: update 5.016 → 5.018
Reported by: portscout
8f238ff |
Tuesday, 8 Aug 2023
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01:15 Yuri Victorovich (yuri)
cad/verilator: Update 5.012 → 5.014
Reported by: portscout
32e3e5d |
Tuesday, 24 Jan 2023
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03:57 Yuri Victorovich (yuri)
cad/verilator: Update 5.004 → 5.006
Reported by: portscout
452499a |
Tuesday, 27 Dec 2022
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07:50 Yuri Victorovich (yuri)
cad/verilator: Update 5.002 -> 5.004
Reported by: portscout
7148bd0 |
Sunday, 30 Oct 2022
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19:42 Yuri Victorovich (yuri)
cad/verilator: Update 4.228 -> 5.002
Reported by: portscout
e12bc69 |
Monday, 20 Jun 2022
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20:57 Yuri Victorovich (yuri)
cad/verilator: Update 4.222 -> 4.224
Reported by: portscout
dd527e7 |
Tuesday, 3 May 2022
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23:34 Yuri Victorovich (yuri)
cad/verilator: Update 4.220 -> 4.222
Reported by: portscout
b8d8eb4 |
Thursday, 21 Oct 2021
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00:46 Yuri Victorovich (yuri)
cad/verilator: Update 4.212 -> 4.214
Reported by: portscout
f8d93a6 |
Monday, 13 Sep 2021
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22:29 Yuri Victorovich (yuri)
cad/verilator: Update 4.210 -> 4.212
Project doesn't distribute tarballs any more in favor of GitHub
tags.
6453e58 |
Friday, 18 Jun 2021
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17:16 Yuri Victorovich (yuri)
cad/verilator: Update 4.202 -> 4.204
a6079c8 |
Saturday, 24 Apr 2021
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22:18 Yuri Victorovich (yuri)
cad/verilator: Update 4.200 -> 4.202
808dd5a |
Tuesday, 15 Sep 2020
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06:05 yuri
cad/verilator: Update 4.040 -> 4.100
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Friday, 11 Sep 2020
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20:13 yuri
cad/verilator: Add options INSTALL_DBG_EXECUTABLES and LEAK_CHECKS
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Saturday, 23 May 2020
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19:04 yuri
cad/verilator: Update 4.028 -> 4.034
PR: 243698
Approved by: kevinz5000@gmail.com (maintainer's timeout; 110 days)
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Sunday, 5 Jan 2020
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08:00 yuri
cad/verilator: Update 4.020 -> 4.024
PR: 243107
Approved by: kevinz5000@gmail.com (maintainer)
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Saturday, 19 Oct 2019
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22:07 yuri
cad/verilator: Update 4.008 -> 4.020
PR: 241346
Approved by: kevinz5000@gmail.com (maintainer)
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Sunday, 27 Jan 2019
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12:25 swills
cad/verilator: update to 4.008
PR: 235228
Approved by: kevinz5000@gmail.com (maintainer)
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Thursday, 17 Jan 2019
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23:27 swills
cad/verilator: create port
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.
WWW: https://www.veripool.org/projects/verilator/wiki/Intro
PR: 230761
Submitted by: Kevin Zheng <kevinz5000@gmail.com>
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Number of commits found: 21 |