notbugAs an Amazon Associate I earn from qualifying purchases.
Want a good read? Try FreeBSD Mastery: Jails (IT Mastery Book 15)
Want a good monitor light? See my photosAll times are UTC
Ukraine
This referral link gives you 10% off a Fastmail.com account and gives me a discount on my Fastmail account.

Get notified when packages are built

A new feature has been added. FreshPorts already tracks package built by the FreeBSD project. This information is displayed on each port page. You can now get an email when FreshPorts notices a new package is available for something on one of your watch lists. However, you must opt into that. Click on Report Subscriptions on the right, and New Package Notification box, and click on Update.

Finally, under Watch Lists, click on ABI Package Subscriptions to select your ABI (e.g. FreeBSD:14:amd64) & package set (latest/quarterly) combination for a given watch list. This is what FreshPorts will look for.

non port: cad/verilator/pkg-descr

Number of commits found: 2

Wednesday, 7 Sep 2022
21:58 Stefan Eßer (se) search for other commits by this committer
Remove WWW entries moved into port Makefiles

Commit b7f05445c00f has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.

This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.

Approved by:		portmgr (tcberner)
commit hash: fb16dfecae4a6efac9f3a78e0b759fb7a3c53de4 commit hash: fb16dfecae4a6efac9f3a78e0b759fb7a3c53de4 commit hash: fb16dfecae4a6efac9f3a78e0b759fb7a3c53de4 commit hash: fb16dfecae4a6efac9f3a78e0b759fb7a3c53de4 fb16dfe
Thursday, 17 Jan 2019
23:27 swills search for other commits by this committer
cad/verilator: create port

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

WWW: https://www.veripool.org/projects/verilator/wiki/Intro

PR:		230761
Submitted by:	Kevin Zheng <kevinz5000@gmail.com>
Original commitRevision:490609 

Number of commits found: 2