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Port details
silice Language that simplifies prototyping and writing algorithms for FPGAs
g20221229_1 cad on this many watch lists=0 search for ports that depend on this port Find issues related to this port Report an issue related to this port View this port on Repology. pkg-fallout g20221229_1Version of this port present on the latest quarterly branch.
Maintainer: yuri@FreeBSD.org search for ports maintained by this maintainer
Port Added: 2023-01-08 09:42:33
Last Update: 2023-04-23 09:09:58
Commit Hash: 8d3e020
License: GPLv3
WWW:
https://github.com/sylefeb/Silice
Description:
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Homepage    cgit ¦ Codeberg ¦ GitHub ¦ GitLab ¦ SVNWeb - no subversion history for this port

Manual pages:
FreshPorts has no man page information for this port.
pkg-plist: as obtained via: make generate-plist
Expand this list (114 items)
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  1. /usr/local/share/licenses/silice-g20221229_1/catalog.mk
  2. /usr/local/share/licenses/silice-g20221229_1/LICENSE
  3. /usr/local/share/licenses/silice-g20221229_1/GPLv3
  4. bin/silice
  5. bin/silice-make.py
  6. share/silice/frameworks/boards/README.md
  7. share/silice/frameworks/boards/bare/bare.sh
  8. share/silice/frameworks/boards/bare/bare.v
  9. share/silice/frameworks/boards/bare/board.json
  10. share/silice/frameworks/boards/boards.json
  11. share/silice/frameworks/boards/crosslink_nx_evn/board.json
  12. share/silice/frameworks/boards/crosslink_nx_evn/crosslink_nx_evn.pdc
  13. share/silice/frameworks/boards/crosslink_nx_evn/crosslink_nx_evn.sh
  14. share/silice/frameworks/boards/crosslink_nx_evn/crosslink_nx_evn.v
  15. share/silice/frameworks/boards/de10nano/board.json
  16. share/silice/frameworks/boards/de10nano/build.sdc
  17. share/silice/frameworks/boards/de10nano/de10nano.v
  18. share/silice/frameworks/boards/de10nano/pins.tcl
  19. share/silice/frameworks/boards/ecpix5/board.json
  20. share/silice/frameworks/boards/ecpix5/ecpix5.lpf
  21. share/silice/frameworks/boards/ecpix5/ecpix5.v
  22. share/silice/frameworks/boards/fomu/board.json
  23. share/silice/frameworks/boards/fomu/fomu-hacker.pcf
  24. share/silice/frameworks/boards/fomu/fomu-hacker.sh
  25. share/silice/frameworks/boards/fomu/fomu-pvt1.pcf
  26. share/silice/frameworks/boards/fomu/fomu-pvt1.sh
  27. share/silice/frameworks/boards/fomu/fomu.v
  28. share/silice/frameworks/boards/formal/board.json
  29. share/silice/frameworks/boards/formal/formal.sh
  30. share/silice/frameworks/boards/formal/formal.v
  31. share/silice/frameworks/boards/icarus/board.json
  32. share/silice/frameworks/boards/icarus/icarus.sh
  33. share/silice/frameworks/boards/icarus/icarus.v
  34. share/silice/frameworks/boards/icebitsy/board.json
  35. share/silice/frameworks/boards/icebitsy/icebitsy.pcf
  36. share/silice/frameworks/boards/icebitsy/icebitsy.v
  37. share/silice/frameworks/boards/icebreaker/board.json
  38. share/silice/frameworks/boards/icebreaker/icebreaker.pcf
  39. share/silice/frameworks/boards/icebreaker/icebreaker.sh
  40. share/silice/frameworks/boards/icebreaker/icebreaker.v
  41. share/silice/frameworks/boards/icestick/board.json
  42. share/silice/frameworks/boards/icestick/icestick.pcf
  43. share/silice/frameworks/boards/icestick/icestick.sh
  44. share/silice/frameworks/boards/icestick/icestick.v
  45. share/silice/frameworks/boards/littlebee/board.json
  46. share/silice/frameworks/boards/littlebee/littlebee.cst
  47. share/silice/frameworks/boards/littlebee/littlebee.sh
  48. share/silice/frameworks/boards/littlebee/littlebee.v
  49. share/silice/frameworks/boards/mch2022/board.json
  50. share/silice/frameworks/boards/mch2022/mch2022.pcf
  51. share/silice/frameworks/boards/mch2022/mch2022.sh
  52. share/silice/frameworks/boards/mch2022/mch2022.v
  53. share/silice/frameworks/boards/minimal/board.json
  54. share/silice/frameworks/boards/minimal/minimal.sh
  55. share/silice/frameworks/boards/minimal/minimal.v
  56. share/silice/frameworks/boards/mojov3/board.json
  57. share/silice/frameworks/boards/mojov3/mojov3.ucf
  58. share/silice/frameworks/boards/mojov3/mojov3.v
  59. share/silice/frameworks/boards/orangecrab/board.json
  60. share/silice/frameworks/boards/orangecrab/orangecrab.sh
  61. share/silice/frameworks/boards/orangecrab/orangecrab.v
  62. share/silice/frameworks/boards/orangecrab/pinout.lpf
  63. share/silice/frameworks/boards/riegel/board.json
  64. share/silice/frameworks/boards/riegel/riegel.pcf
  65. share/silice/frameworks/boards/riegel/riegel.v
  66. share/silice/frameworks/boards/techgraph/board.json
  67. share/silice/frameworks/boards/techgraph/techgraph.sh
  68. share/silice/frameworks/boards/techgraph/techgraph.v
  69. share/silice/frameworks/boards/ulx3s/board.json
  70. share/silice/frameworks/boards/ulx3s/ulx3s.lpf
  71. share/silice/frameworks/boards/ulx3s/ulx3s.sh
  72. share/silice/frameworks/boards/ulx3s/ulx3s.v
  73. share/silice/frameworks/boards/verilator/board.json
  74. share/silice/frameworks/boards/verilator/verilator.sh
  75. share/silice/frameworks/boards/verilator/verilator.v
  76. share/silice/frameworks/libraries/memory_ports.si
  77. share/silice/frameworks/libraries/riscv/ice-v-dual/config_c.ld
  78. share/silice/frameworks/libraries/riscv/ice-v-dual/crt0.s
  79. share/silice/frameworks/libraries/riscv/ice-v-dual/header.h
  80. share/silice/frameworks/libraries/riscv/ice-v-dual/riscv-soc.si
  81. share/silice/frameworks/libraries/riscv/ice-v/config_c.ld
  82. share/silice/frameworks/libraries/riscv/ice-v/crt0.s
  83. share/silice/frameworks/libraries/riscv/ice-v/header.h
  84. share/silice/frameworks/libraries/riscv/ice-v/riscv-soc.si
  85. share/silice/frameworks/libraries/riscv/riscv-compile.lua
  86. share/silice/frameworks/templates/bram_generic.v.in
  87. share/silice/frameworks/templates/bram_wmask_byte.v.in
  88. share/silice/frameworks/templates/brom_generic.v.in
  89. share/silice/frameworks/templates/dualport_bram_altera.v.in
  90. share/silice/frameworks/templates/dualport_bram_generic.v.in
  91. share/silice/frameworks/templates/dualport_bram_wmask_byte.v.in
  92. share/silice/frameworks/templates/simple_dualport_bram_generic.v.in
  93. share/silice/frameworks/templates/simple_dualport_bram_wmask_byte.v.in
  94. share/silice/frameworks/templates/simple_dualport_bram_wmask_half_bytes.v.in
  95. share/silice/frameworks/verilator/README.md
  96. share/silice/frameworks/verilator/SPIScreen.cpp
  97. share/silice/frameworks/verilator/SPIScreen.h
  98. share/silice/frameworks/verilator/VgaChip.cpp
  99. share/silice/frameworks/verilator/VgaChip.h
  100. share/silice/frameworks/verilator/display.cpp
  101. share/silice/frameworks/verilator/display.h
  102. share/silice/frameworks/verilator/flyover_simul.gif
  103. share/silice/frameworks/verilator/sdr_sdram.cpp
  104. share/silice/frameworks/verilator/sdr_sdram.h
  105. share/silice/frameworks/verilator/verilator_bare.cpp
  106. share/silice/frameworks/verilator/verilator_data.cpp
  107. share/silice/frameworks/verilator/verilator_data.h
  108. share/silice/frameworks/verilator/verilator_sdram.cpp
  109. share/silice/frameworks/verilator/verilator_spiscreen.cpp
  110. share/silice/frameworks/verilator/verilator_vga.cpp
  111. share/silice/frameworks/verilator/verilator_vga_sdram.cpp
  112. @owner
  113. @group
  114. @mode
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Dependency lines:
  • silice>0:cad/silice
To install the port:
cd /usr/ports/cad/silice/ && make install clean
To add the package, run one of these commands:
  • pkg install cad/silice
  • pkg install silice
NOTE: If this package has multiple flavors (see below), then use one of them instead of the name specified above.
PKGNAME: silice
Flavors: there is no flavor information for this port.
distinfo:
TIMESTAMP = 1673143292 SHA256 (sylefeb-Silice-g20221229-6a2beda_GH0.tar.gz) = 5577d91ccac7e26204a034d262faa6107bbf06fdefe7107b3a5670364384f59c SIZE (sylefeb-Silice-g20221229-6a2beda_GH0.tar.gz) = 42949179

Expand this list (6 items)

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SHA256 (sylefeb-LibSL-small-b1942d5_GH0.tar.gz) = dbea9ba30c4e40e3e9e6da840e90eb9e0a91b0355dc3ae0e72602d70d718d8fd SIZE (sylefeb-LibSL-small-b1942d5_GH0.tar.gz) = 72760 SHA256 (sylefeb-tinygpus-e6429ac_GH0.tar.gz) = 5e1cdfae1b81402acbeb118f350537599fd74cb8e2bc486ea6cb753ffe8f0d05 SIZE (sylefeb-tinygpus-e6429ac_GH0.tar.gz) = 1435993 SHA256 (ultraembedded-fat_io_lib-0ef5c2b_GH0.tar.gz) = a88b5a3b0707931e7b2689d8f886b7dac53c9c4262aa9b3938d91a065c114079 SIZE (ultraembedded-fat_io_lib-0ef5c2b_GH0.tar.gz) = 52464

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Packages (timestamps in pop-ups are UTC):
silice
ABIaarch64amd64armv6armv7i386powerpcpowerpc64powerpc64le
FreeBSD:13:latest-g20221229_1--g20221229_1---
FreeBSD:13:quarterly-g20221229_1--g20221229_1-g20221229_1-
FreeBSD:14:latest-g20221229_1--g20221229_1---
FreeBSD:14:quarterly-g20221229_1--g20221229_1-g20221229_1-
FreeBSD:15:latest-g20221229_1n/a-n/a-g20221229_1-
Dependencies
NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.
Build dependencies:
  1. bash : shells/bash
  2. java : java/openjdk17
  3. cmake : devel/cmake-core
  4. python3.9 : lang/python39
Test dependencies:
  1. python3.9 : lang/python39
Runtime dependencies:
  1. py39-edalize>0 : cad/py-edalize@py39
  2. java : java/openjdk17
  3. python3.9 : lang/python39
There are no ports dependent upon this port

Configuration Options:
No options to configure
Options name:
cad_silice
USES:
cmake:noninja python shebangfix
FreshPorts was unable to extract/find any pkg message
Master Sites:
Expand this list (1 items)
Collapse this list.
  1. https://codeload.github.com/sylefeb/Silice/tar.gz/6a2beda?dummy=/
Collapse this list.

Number of commits found: 2

Commit History - (may be incomplete: for full details, see links to repositories near top of page)
CommitCreditsLog message
g20221229_1
23 Apr 2023 09:09:58
commit hash: 8d3e020ed032a8db00208994d0db646de7dc6f5bcommit hash: 8d3e020ed032a8db00208994d0db646de7dc6f5bcommit hash: 8d3e020ed032a8db00208994d0db646de7dc6f5bcommit hash: 8d3e020ed032a8db00208994d0db646de7dc6f5b files touched by this commit
Gerald Pfeifer (gerald) search for other commits by this committer
*: Bump PORTREVISIONs for math/mpc update to 1.3.1
g20221229
08 Jan 2023 09:40:50
commit hash: d726e22a21003c3b6f709d2d3b33adf8e652807ecommit hash: d726e22a21003c3b6f709d2d3b33adf8e652807ecommit hash: d726e22a21003c3b6f709d2d3b33adf8e652807ecommit hash: d726e22a21003c3b6f709d2d3b33adf8e652807e files touched by this commit
Yuri Victorovich (yuri) search for other commits by this committer
cad/silice: New port: Language that simplifies prototyping and writing
algorithms for FPGAs

Number of commits found: 2