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SVNWeb
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Number of commits found: 19 |
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Wed, 7 Sep 2022
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[ 21:10 Stefan Eßer (se)  ]    b7f0544 (Only the first 10 of 27931 ports in this commit are shown above.  )
Add WWW entries to port Makefiles
It has been common practice to have one or more URLs at the end of the
ports' pkg-descr files, one per line and prefixed with "WWW:". These
URLs should point at a project website or other relevant resources.
Access to these URLs required processing of the pkg-descr files, and
they have often become stale over time. If more than one such URL was
present in a pkg-descr file, only the first one was tarnsfered into
the port INDEX, but for many ports only the last line did contain the
port specific URL to further information.
There have been several proposals to make a project URL available as
a macro in the ports' Makefiles, over time.
(Only the first 15 lines of the commit message are shown above )
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Wed, 20 Jul 2022
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[ 14:20 Tobias C. Berner (tcberner) ] b46abf8 (Only the first 10 of 74 ports in this commit are shown above. )
cad: remove 'Created by' lines
A big Thank You to the original contributors of these ports:
* AMAKAWA Shuhei <amakawa@jp.FreeBSD.org>
* Alexey Dokuchaev <danfe@FreeBSD.org>
* Anders Andersson <anders@hack.org>
* Bruce M Simpson <bms@FreeBSD.org>
* Christoph Moench-Tegeder <cmt@FreeBSD.org>
* David Yeske <dyeske@gmail.com>
* Diane Bruce <db@db.net>
* Joachim Strombergson <watchman@ludd.ltu.se>
* Johnny Sorocil <jsorocil@gmail.com>
* Julian Jenkins <kaveman@magna.com.au>
* Marc Fonvieille <blackend@FreeBSD.org> (Only the first 15 lines of the commit message are shown above )
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Tue, 6 Apr 2021
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[ 14:31 Mathieu Arnold (mat) ] 305f148 (Only the first 10 of 29333 ports in this commit are shown above. )
Remove # $FreeBSD$ from Makefiles.
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Wed, 19 Jun 2019
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[ 10:16 danfe ]  
- Fix the checks to avoid using `sys/dir.h' and thus undeprecate
- Define LICENSE (GPLv2) and install supplied documentation files
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Wed, 12 Jun 2019
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[ 06:52 bapt ]
Mark as deprecated a bunch of abandonware using sys/dir.h
sys/dir.h is going to be phased out soon, so mark as deprecated non maintained
abandonware using it.
PR: 21519
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Mon, 9 Jun 2014
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[ 11:21 olgeni ] (Only the first 10 of 120 ports in this commit are shown above. )
Remove indefinite articles and trailing periods from COMMENT, plus
minor COMMENT typos and surrounding whitespace fixes. Categories A-C.
CR: D196
Approved by: portmgr (bapt)
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Sun, 1 Jun 2014
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[ 14:48 ohauer ]
- USE_(BZIP2|XZ) -> USES=tar:(bzip2|xz)
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Thu, 27 Feb 2014
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[ 13:43 ehaupt ]
Support staging
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Fri, 20 Sep 2013
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[ 15:58 bapt ] (Only the first 10 of 103 ports in this commit are shown above. )
Add NO_STAGE all over the place in preparation for the staging support (cat:
cad)
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Thu, 16 Jun 2011
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[ 10:41 bapt ]
Point to the new home
Make it fetchable again
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Mon, 27 Oct 2008
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[ 15:59 tabthorpe ]
- Reassign to ports
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Thu, 23 Aug 2007
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[ 04:00 tabthorpe ] (Only the first 10 of 58 ports in this commit are shown above. )
- change maintainer address on ports I maintain
Approved by: clsung (mentor)
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Sat, 21 Jul 2007
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[ 01:21 ijliao ]
'actually' pass maintainership
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[ 01:20 ijliao ]
upgrade to 2.12.a
pass maintainership to submitter
PR: 114768
Submitted by: Thomas Abthorpe <thomas@goodking.ca>
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Thu, 3 Aug 2006
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[ 03:26 clsung ]
- maintainer is a committer
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Fri, 20 Jan 2006
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[ 14:18 arved ]
Fix build on sparc
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Thu, 19 Jan 2006
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[ 23:31 kris ]
BROKEN on sparc64: Does not compile
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Wed, 4 Jan 2006
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[ 05:56 edwin ]
Fix maintainership (set to submitter)
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Thu, 29 Dec 2005
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[ 03:48 edwin ]
[NEW PORT] cad/gplcver: A Verilog HDL simulator
GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
It also implements some of the 2001 P1364 standard features
including all three PLI interfaces (tf_, acc_ and vpi_) as
defined in the 2001 Language Reference Manual (LRM).
Verilog is the name for both a language for describing
electronic hardware called a hardware description language
(HDL) and the name of the program that simulates HDL circuit
descriptions to verify that described circuits will function
correctly when the are constructed. Verilog is used only
for describing digital logic circuits. Other HDLs such as
Spice are used for describing analog circuits. There is an
IEEE standard named P1364 that standardizes the Verilog HDL
and the behavior of Verilog simulators. Verilog is officially
defined in the IEEE P1364 Language Reference Manual (LRM)
that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach
digital circuit design using Verilog.
WWW: http://www.pragmatic-c.com/gpl-cver/
PR: ports/80968
Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>
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Number of commits found: 19 |
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